Then include the forward saif file in your testbench to generate a backward annotated saif file. Using Design Compiler, you first need to generate a forward saif file. Note that through this procedure, you also can get the area and timing slack estimation. First, you will synthesize it, and then you can derive the power estimation of the synthesized circuit. This tutorial shows how to get power estimation at the gate level through logic simulation with test vectors supplied by users for a 4-bit counter, which is described in the behavioral level, using Primetime-PX or Power Compiler. Author: Jeannette Djigbenou Frequently Asked Questions
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